FIG. 1 illustrates a typical random access memory architecture. The memory 10 includes a matrix or array 12 of storage cells 14 having a capacity defined by the number of rows and columns in the array. The array 12 illustrated in FIG. 1 has a capacity of 2.sup.N .times.2.sup.M where N indicates the number address lines devoted to row selection and M indicates the number of address lines devoted to column selection.
To read data from or write data to the array 12, a row address is input to and decoded in row decoder 16 to select a row or word line 18. This activates all of the memory cells 14 in the selected row. Simultaneously, a column address is input to and decoded in column decoder 20 to select a column or bit line 22. The memory cell 14 located at the intersection of the selected word and bit lines is then accessed.
The memory 10 also includes an input/output (I/O) control circuit 24 which is used to control the flow of data into or out of the memory array 12. A data bus 26 having Q+1 total data lines is coupled to the I/O control circuit 24 and may be used to write to or read from the array 12. Control signals including a chip enable (CE) signal, an output enable (OE) signal and a write enable (WE) signal are provided to the I/O control circuit 24 to control the direction of data flow between the data bus 26 and the array 12. A write operation may be controlled by the CE and WE signals. When reading the device, both the OE and CE signals may need to be asserted while WE is deasserted.
The "depth" of a memory array such as array 12 refers to the width of the data bus (D.sub.0 -D.sub.Q) which the array is capable of interfacing with. For example, a memory array which is 16-bits deep refers to an array which is organized so as to interface with a 16-bit data bus (i.e., a data bus where Q=15). In such an architecture, the memory array is organized so as to allow access to 16 memory cells at a time. In contrast, an 8-bit deep array is organized so as to allow access to only 8 memory cells at a time. Despite this depth difference, however, the physical size of the memory arrays in the 16-bit deep memory and the 8-bit deep memory may be the same. For example, a memory device having an array of 128K memory cells may be organized as a 16K.times.8 (16K words of 8-bits each) device or an 8X.times.16 (8K words of 16-bits each) device.
Because various applications require memory devices having different depths, memory device manufacturers are required to provide various memory devices which may have memory arrays of similar physical size but which are organized differently. To reduce design and fabrication costs, such manufacturers often design these memory devices so that the same chip layout may be used. That is, a common layout is used for memory devices to be organized as N-bit deep devices as is used for memory devices to be organized as 2N-bit deep devices. Additional decoding circuitry is provided on the chip (e.g., at the periphery of the array) to allow control of the memory depth according to whether a 2N-bit deep architecture or an N-bit architecture is desired.
FIG. 2 shows a typical scheme for controlling memory depth. Assume that a memory device has an array organized into a number of groups of columns. Each column contains a number of rows of memory cells. In general, the address decoding circuitry will be arranged so that high order address bits are used to select a particular group and column while low order address bits are used to select a particular row. For example, in the case of a 128K memory array arranged as 8 groups of 4 columns of memory cells, each column having 256 rows, address bits A.sub.10 -A.sub.12 may be used to select one of the 8 groups, bits A.sub.8 and A.sub.9 may be used to select one of the four columns within the selected group and bits A.sub.0 -A.sub.7 may be used to select one of the 256 rows of the selected column.
It will be appreciated that the above example would be suitable for a 128K memory device organized as 8K.times.16. A total of 8K (=2.sub.13) words, each 16-bits long, are addressable using the above decoding scheme. If the same decoding logic were to be used for a 16K.times.8 implementation, however, an additional level of decoding would be required. For example, as shown in FIG. 2, each group select signal (Grp [0]-Grp [7]) from a group decode circuit could be applied to decoder logic 40 along with an additional address bit (Add+) to uniquely decode a sub-group within each group. Each subgroup would be 8-bits wide, thus permitting access to 16K words total.
Additional decoding schemes such as that illustrated in FIG. 2 are commonly employed by memory manufacturers wishing to use common layouts for N-bit and 2N-bit memory architectures. Some of the memory devices so manufactured will be utilized as N-bit architectures and will thus employ the extra level of decoding while other memory devices will be utilized as 2N-bit architectures and will not employ the extra decoding logic. For the N-bit devices then, the extra decoding logic represents additional chip area and cost and could also cause a penalty in access time. Nevertheless, such schemes are common because of the desire to fabricate memory devices using common layout schemes.
In view of the above, it would be desirable to implement a circuit for controlling memory depth in a memory device which eliminated the need for the extra decoding circuitry described above.